Screen printing electrical contacts to nanostructured areas

ABSTRACT

A process is provided for contacting a nanostructured surface. The process may include (a) providing a substrate having a nanostructured material on a surface, (b) passivating the surface on which the nanostructured material is located, (c) screen printing onto the nanostructured surface and (d) firing the screen printing ink at a high temperature. In some embodiments, the nanostructured material compromises silicon. In some embodiments, the nanostructured material includes silicon nanowires. In some embodiments, the nanowires are around 150 nm, 250 nm, or 400 nm in length. In some embodiments, the nanowires have a diameter range between about 30 nm and about 200 nm. In some embodiments, the nanowires are tapered such that the base is larger than the tip. In some embodiments, the nanowires are tapered at an angle of about 1 degree, about 3 degrees, or about 10 degrees. In some embodiments, a high temperature can be approximately 700 C, 750 C, 800 C, or 850 C.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 120 as a continuationof U.S. patent application Ser. No. 15/622,422, titled “SCREEN PRINTINGELECTRICAL CONTACTS TO NANOSTRUCTURED AREAS,” filed Jun. 14, 2017, whichin turn claims priority under 35 U.S.C. § 120 as a continuation of U.S.patent application Ser. No. 14/338,752, titled “SCREEN PRINTINGELECTRICAL CONTACTS TO NANOWIRE AREAS,” filed Jul. 23, 2014, which inturn claims priority as a continuation of international applicationPCT/US2013/025958, filed Feb. 13, 2013, which claims priority to U.S.provisional patent application No. 61/598,717 filed Feb. 14, 2012. Theseapplications are each incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

Nanowire arrays are seeing increasing use in a variety of applications.See. e.g., U.S. Pat. No. 8,143,143, “Process for Fabricating NanowireArrays.” issued Mar. 27, 2012. An exemplary silicon nanowire array mayinclude a collection of silicon nanowires, on the order of 100 nm indiameter, on the order of several micrometers in height, and ofapproximately cylindrical or frustoconical shape. The axes of thenanowires run approximately parallel to each other. Each is attached atan end to a silicon substrate and is very roughly perpendicular to thatsubstrate.

A process for fabricating nanowire arrays is described in U.S. Pat. No.8,143,143. In this process, one deposits nanoparticles and a metal filmonto the substrate in such a way that the metal is present and touchessilicon where etching is desired, and is blocked from touching siliconor not present elsewhere. One submerges the metallized substrate into anetchant aqueous solution comprising hydrofluoric acid (HF) and anoxidizing agent. In this way, arrays of nanowires with controlleddiameter and length are produced.

Relevant information regarding silicon fabrication processes known tothose of skill in the art can be found, for example, in Sami Franssila.Introduction to Microfabrication (John Wiley & Sons 2004), and thereferences cited therein.

A silicon nanowire array can reduce the reflectivity of a solar cellsurface. Other types of nanostructuring can also achieve this effect.

A silicon nanowire array on top of a silicon substrate, can alter theopto-electrical properties of the bulk silicon substrate. For example, asilicon nanowire array reduces the reflection of the silicon substrate,reduces the reflection at off-angles of incidence, and increases theabsorption of the silicon in ways similar to traditional pyramids orlight trapping mechanisms used in solar cells.

Some of the altered optical-electrical properties of silicon nanowirescompared to bulk silicon are beneficial for solar cells. However, inorder to form a solar cell, the two sides of a p-n junction need to beconnected to the outside world. Unfortunately, contacting nanowires isnot always easy.

One device design for nanowire solar cells places vertically alignednanowires on top of a bulk (non-nanostructured) substrate. In thisdesign, the back contact can be made from the backside of the substrate.The front contact, however, is more difficult to make.

For the types of solar cells currently manufactured, not using nanowirearrays, it is common to make contacts by screen printing. Screenprinting is robust, has a high throughput, and is low-cost. The frontand back contacts of a solar cell are typically formed in separatesteps. For most cell designs, silver is applied to the front, andaluminum to the back. For the front, paste is squeezed through astainless steel or polyester fine metal mesh screen with an adjustableand finely controlled force delivered through metal or polymer squeegee.The screen defines a comb-like (finger line array and crossed bus bars)pattern designed to provide sufficient conductivity while minimizingoptical shading from the metal lines. The paste is then dried attemperatures of 100-200 C to drive off organic solvents and fired ataround 800 C to diffuse in the metal to establish a low contactresistance junction. For the back, an aluminum based paste is screenprinted on the rear surface, establishing electrical contact andfunctioning as a back surface field. The aluminum is applied as a pastesqueezed through a fine mesh screen, then fired at high temperatures todrive off organic solvents and diffuse in the aluminum to establish alow contact resistance junction. Although a continuous contact willresult in lower resistance, commercial wafers utilize a back contactwith an embedded mesh structure to reduce paste usage and minimize waferwarping during the subsequent high temperature processing steps. Thepattern is defined in the screen by photolithography, although laser cutmetal stencils may be utilized for smaller line widths. Automatic screenprinters are available that are capable of in-line, continuous operationwith high throughput. These machines accept wafers from packs, cassettesor a belt line, place them with sufficient accuracy under the screen anddeliver the printed wafers to the belt line. Detailed methods for screenprinting are described in reference (1).

One of ordinary skill in the art would expect that screen printing onnanowires would be difficult. For one, the nanowires may break or bendwhen the squeegee is moved across the surface of the cell to removeexcess screen printing paste. In addition, one of ordinary skill in theart may not expect the nanowires to survive the high temperature firerequired to drive off the organic materials in the pastes. Although thepresent assignee and others have contacted nanowire arrays with otherprocesses such as electrochemical deposition (6) and sputtering, screenprinting is the dominate process in solar cell manufacturing and iscost-effective. Hence developing a nanowire array that can be contactedvia screen printing is of commercial importance.

SUMMARY OF THE INVENTION

A process is provided for contacting a nanostructured surface. In thatprocess, a substrate is provided having a nanostructured material on asurface. A conductor is applied to the nanostructured surface withscreen printing.

In one aspect, the present disclosure relates to a process including:(a) providing a substrate having a nanostructured material on a surface.(b) screen printing onto the nanostructured surface and (c) firing thescreen printing ink at a high temperature. In some embodiments, thenanostructured material compromises silicon. In some embodiments, thenanostructured material includes silicon nanowires. In some embodiments,the nanowires are around 150 nm, 250 nm, or 400 nm in length. In someembodiments, the nanowires have a diameter range between about 30 nm andabout 200 nm. In some embodiments, the nanowires are tapered such thatthe base is larger than the tip. In some embodiments, the nanowires aretapered at an angle of about 1 degree, about 3 degrees, or about 10degrees. In some embodiments, a high temperature can be approximately700 C, 750 C, 800 C, or 850 C.

Another aspect of the present disclosure relates to a siliconnanostructured p-n junction with screen printed contacts contacting thenanostructured side. In some embodiments, the p-n junction can be usedas a solar cell. In some embodiments, the nanostructured side includes ananowire array. In some embodiments, both sides of the substrate havenanowires and both sides are contacted through screen printing. In someembodiments, the junction is below the nanowire array. In someembodiments, the nanowire array is coated with a passivating layer. Insome embodiments, the passivating layer surrounding the nanowireincludes aluminum oxide. In some embodiments, the passivating layersurrounding the nanowire is silicon dioxide. In some embodiments, thepassivating layer surrounding the nanowire can be silicon nitride.

Another aspect of the present disclosure relates to a silicon nanowirearray passivated with silicon nitride. In some embodiments, the siliconnitride can be deposited using plasma enhanced CVD (PECVD).

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 depicts an edge view scanning electron micrograph of siliconnanowires coated with alumina.

FIG. 2 depicts an example of a process flow for forming screen printednanowire solar cells on alumina coated nanowires from exemplary process1.

FIG. 3 depicts an alternative example of a process flow for formingscreen printed nanowire solar cells where a plasma enhanced chemicalvapor deposition (PECVD)-silicon nitride passivation layer covers thenanowire array prior to screen printing, from exemplary process 3.

FIG. 4 depicts a schematic of a screen printed solar cell.

DETAILED DESCRIPTION OF THE INVENTION

Before describing the present invention in detail, it is to beunderstood that this invention is not limited to specific solvents,materials, or device structures, as such may vary. It is also to beunderstood that the terminology used herein is for the purpose ofdescribing particular embodiments only, and is not intended to belimiting.

In this process, a substrate is provided having a nanostructuredmaterial on a surface. The substrate is then subjected to standardscreen printing processes. Screen printing is where screen printing ink(or paste) is squeezed through a stainless steel or polyester fine metalmesh screen with an adjustable and finely controlled force deliveredthrough metal or polymer squeegee. The screen defines a comb-like(finger line array and crossed bus bars) pattern designed to providesufficient conductivity while minimizing optical shading from the metallines. The paste is then dried at temperatures of 100-200 C to drive offorganic solvents and fired at around 800 C to diffuse in the metal toestablish a low contact resistance junction.

Without wishing to be bound by theory, it is believed that the geometryof the described nanowire arrays permit screen printing with a standardscreen printing process, directly onto the nanowire array. Inparticular, relatively short nanowires are desired for sufficientanti-reflection and scattering properties. The described nanowires usedin the described solar cells are in the range of 150-450 nm in length,in some embodiments about 250 nm in length, compared to other nanowirearrays reported in the literature where the nanowire arrays are over amicron and often several microns. Furthermore, the disclosed nanowirearrays are dense. Roughly one third to one half of the volume of thenanowire array is silicon with the remaining volume being a passivationlayer and air. The density of the nanowire array and the shorter wiresimprove the structural integrity of the nanowires during the mechanicaland thermal stresses of the screen printing process.

In one aspect of the present disclosure, the substrate andnanostructures are comprised of materials other than silicon. Numerousmethods of creating nanostructures on the substrate are contemplatedincluding vapor liquid solid processes, laser chemical vapor deposition,reactive ion etching, and metal enhanced etching.

A variety of materials maybe deposited according to methods of thepresent disclosure depending on the device which is being manufactured.The current disclosure is not meant to be limited to use with certainmaterials. Some thin film device components which may be deposited withthe described processes include metal electrodes for solar cells,interconnects and bus bars for solar cells, and electrodes for sensors,thin film batteries, and transistors.

In a further aspect of the present disclosure, an optoelectronic deviceis provided. The optoelectronic device includes (a) a substrate. (b) ananostructured area on a first surface of the substrate, (c) an optionalinsulating layer atop the first surface, and (f) a conductor atop theoptional insulating layer and nanostructured area, where the conductorwas applied by screen printing. The conductor may be, for example, inthe form of a grid, and consist of silver, aluminum, copper, or alloysincluding these metals.

Exemplary Process 1

An exemplary process of this embodiment is summarized in FIG. 2. N-typesilicon material with a resistivity of 1 ohm-cm is selected having asurface with a (100) crystallographic orientation.

The first step is to form a nanowire array (step 200). The formation ofnanowire in Exemplary Process 1 is as follows: the first step is todeposit 50-170 A of silver which will be used for metal enhancedetching. The wafer is loaded into a sputtering chamber and silver issputtered at a rate of 2-4 Å/s, a base pressure of <1e-6 Torr, and anargon pressure of 2e-3 Torr. The properties of the silver film ascontrolled by deposition rate, pressure, and thickness control thenanowire diameter, density, and taper.

The next step is the nanowire formation in an oxygen/HF bath. After thesample is removed from the sputtering chamber, it is placed in a dilutehydrofluoric acid (HF) bath. The bath contains 10 parts volume water to1 part volume HF. The sample is etched in the HF bath for 10 minutesduring which time oxygen is bubbled vigorously through the HF using aperforated plastic tube. The longer the sample is left in the bath, thelonger the nanowires. For effective screen printing we hypothesis thatthe nanowires should be between 150 and 750 nm in length, thiscorresponds to an etch time between approximately 3 minutes and 20minutes.

The concentration of the HF as well as the amount of oxygen present isone way to taper the nanowire. A slower etch will allow some verticaletching of the silicon and will lead to nanowire arrays with a slighttaper. i.e., the nanowire has a larger diameter at its base than at thetop of the nanowire. Generally, the nanowires have a diameter of about30 nm to about 200 nm. The tapering of the nanowires can be about 1 toabout 10 degrees, for example, about one degree, about three degrees orabout 10 degrees.

Afterwards, the sample is rinsed three times in deionized water (DI).

The silver is then removed and the sample is cleaned in a series of wetbaths. The first bath is a piranha clean which consists of 4 ml ofsulfuric acid (H₂SO₄) to 1 ml of 30 wt % hydrogen peroxide (H₂O₂) at 70C. Prior to placing the wafer into the piranha, it is stirred for 2minutes. The stirring is then commenced and the wafer is submerged for15 minutes. After the piranha etch, the wafer is cleaned 3 times with DIwater.

The sample is then placed in dilute HF for 30 seconds. This HF solutionhas a volume ratio of 24:1 of water to 49% HF and is at roomtemperature. The wafer is then rinsed three times with DI water.

Next, a traditional 10 minute SC1 clean is done. This is a bath of 5:1:1volume ratio of water, 30 wt % ammonium hydroxide (NH4OH), and 30 wt %hydrogen peroxide and is at 70 C. Again the wafer is rinsed three timesin DI water.

After the SC1 clean an SC2 clean is performed on the wafer. This cleanis a 10 minute soak at 70 C in 5:1:1 volume ratio of water, 37 wt %hydrochloric acid (HCl), 30 wt % hydrogen peroxide. The sample is thenrinsed three times in DI water. Once these steps are complete, ananowire array has been formed.

The next step of the method described in FIG. 2 is to dope the samples,i.e., to dope the junction on the sample (step 202). For this dopingprocess we will first place dopants onto two source wafers. One sourcewafer will dope the front nanowire side of the wafer and will have borondoping. The other source wafer will have phosphorus and will dope theback side of the sample wafer. The source wafers will be used to dopethe sample wafer.

In order to prepare the two source wafers, they are first cleaned withthe piranha, HF, SC1, and SC2 cleans as described above.

Boron is spun onto one source wafer using the boron film spin-ondiffusant B-153 (Filmtronics, Inc., Butler, Pa.). The dopant is spun onusing a 5 second prespin at 500 RPM and then a 15 second spin at 5000RPM.

A small dime size spot of Filmtronics, Inc. (Butler, Pa.) phosphorusfilm spin-on diffusant P-506 is dropped onto the second source wafer.Both source wafers are then baked at 250 C on a hot plate for 10minutes.

Next the stack of wafers used to dope the sample wafer is formed. Theboron source wafer boron is placed boron side up on a quartz disc. Thenthree 525 micron thick spacers of silicon are placed on the edges of thewafer. The sample wafer is then placed nanowire side down on the boronsource wafer, three more spacers are placed on the edges of the wafer,and the final source wafer (the phosphorus-doped source wafer) is placedphosphorus side down facing the non-nanowire side of the sample wafer.

The full stack including the two source wafers, spacers, and samplewafer are then pushed into a furnace tube with argon flowing at 2000standard cubic centimeters per minute (SCCM) from room temperature to1050 C in 1 minute 30 seconds. The furnace is then held at a flow rateof argon of 2000 SCCM and a temperature of 1050 C for 5 minutes, atwhich point 500 SCCMS of oxygen is added to the flow and the temperatureis ramped down at 6 degrees per minute, for 15 minutes. After 15minutes, the oxygen is switched off while the argon is left on and thefurnace is allowed to cool to 745 C. The stack is then pulled out andcooled to room temperature in atmosphere. The sample wafer is removedfrom the stack.

The next step is the back contact. The sample wafer is first cleaned ina 10 minute HF dip with 4 ml of water to 1 ml of HF and rinsed threetimes, step 204 in FIG. 2.

The next step of the method disclosed in FIG. 2 (step 206) is to placealumina passivation via atomic layer deposition (ALD) on the nanowirearray, which provides electrical passivation on the nanowire arrays. Thesamples are placed inside the ALD chamber. The ALD system may be, forexample, a Cambridge Nanotech Savannah 5200 (Cambridge. Mass.). The ALDchamber is preheated to 250 C prior to loading our samples. After thesamples are loaded, the chamber is pumped with a rough pump while aconstant flow of N₂ at 20 SCCMs is introduced into the chamber. Thepressure is around 2200 mTorr with this process. The program is set tomake the process wait until the heaters are at 250 C. Once thetemperature is at 250 C. the program waits another 60 seconds and pulseswater, and then with trimethylaluminum (TMA). An automatic pulse controlprogram is executed alternating between water and TMA for a total of 275cycles.

FIG. 1 depicts an edge view scanning electron micrograph of siliconnanowires coated with alumina. The cleaved edge, labeled 100 in FIG. 1,illustrates the alumina coating.

The next step (step 208) is screen printing the front and back contactswith the paste. One skilled in the art of screen printing will be ableto optimize the screen printing ink and deposition process. Next thefront and back contacts are fired (step 210) using conditions know bythose skilled in the art of screen printing. Peak temperatures generallyare around 700-900 C. Firing with the proper conditions and a properramp profile ensures good contact resistance, good sheet resistance, andlow junction leakage. Exemplary on screen printing conditions are

Exemplary Process 2

A variation on the previously described process is to screen print priorto alumina passivation and then apply alumina passivation after thescreen printed contacts are applied.

Exemplary Process 3

An alternative to the preceding processes is to form nanowire array andthen deposit plasma enhanced chemical vapor deposition (PECVD) siliconnitride (SiN), as shown in FIG. 3. In this flow, the nanowires areformed (step 310), the sample is cleaned (step 320), the junction isformed (step 330), and the sample is then cleaned and the oxide isetched (340). All of these steps are identical to the previous example.However, the next step is to deposit SiN (step 350). This is thepassivation material used in traditional processing, and therefore theidentical screen printing ink deposition (step 360) and firing (step370) as discussed above can be used.

FIG. 4 depicts a schematic of a screen printed solar cell 400. Thescreen printed solar cell 400 includes a substrate 410, an array ofnanowires 415 and a plurality of screen printed contacts 420.

APPLICATIONS

Processes and device designs of the invention may be applied tocontacting silicon nanowire arrays for optoelectronic devices. They maybe employed in devices that utilize the photoelectric or photovoltaiceffect, for example solar cells, photodetectors, photodiodes,phototransistors, photomultipliers and integrated optical circuits.

Processes and designs of the invention may be employed to producedevices made out of or comprising polycrystalline silicon. The inventionencompasses processes and designs, which can be used with anycrystalline orientation of silicon including polysilicon. Polysilicon isa cheaper material than crystalline silicon, but it is typically moredifficult to texture and structure than single crystal silicon due tothe random orientation of the grains. The processes and design of theinvention can likewise be used to contact nanowires in amorphoussilicon.

Arrays of silicon nanowires can be used in applications where thesilicon will be subjected to stress or strain where the nanostructure isable to absorb and relax this stress or strain. For example, nanowirescan act as an interfacial layer between bulk silicon and anothermaterial grown on top, which is not lattice-matched to it.

Processes described in this application are also applicable to lithiumion battery technology. Silicon has been seen as a desirable candidatefor the anode material in lithium ion batteries due to its low dischargepotential and high charge capacity. Its application in the past has beenlimited due to the large change in volume associated with ion insertionand ion extraction. The large amounts of stress and strain that buildsin the silicon results in degradation of the silicon layer resulting ina very short performance lifetime. Nanowires have been pursued due totheir ability to withstand these stress and strains. The fact thatporous silicon (nanopores or micropores) can also be contacted viaprocesses described in this application would enable the fabrication ofanother anode geometry capable of withstanding the stresses and strainsof ion insertion/extraction for lithium ion battery applications.

Processes and designs described in this application may be used tocontact nanostructures, which make silicon into an intermediate bandphotovoltaic material (IBPV). Silicon has an excellent band structurefor IBPV, provided that the strength of particular electronictransitions can be enhanced. One way to do this is to form a dense arrayof silicon nanowires with specific control over the wire diameter,doping and crystallographic orientation. Processes and designs describedin this application may be used for contacting such nanowire arrays.

Processes and designs described in this application may be used tocontact nanostructures formed for the purpose of being able to makeelectrical contact via the processes and designs of this application.

The following references may be relevant to this application: (1) I.Tobias, C. del Canizo, J. Alonso, “Crystalline silicon solar cells andmodules.” Chapter 7 in A. Luque, Handbook of photovoltaic Science andEngineering (John Wiley & Sons 2003). (2) Sami Franssila, Introductionto Microfabrication (2d ed. John Wiley & Sons 2010). (3) K. Kang. W.Cai, “Size and temperature effects on the fracture mechanisms of siliconnanowires: Molecular dynamics simulations,” International Journal ofPlasticity 26, 1387-1401 (2010). (4) B. A. Gozen and O. B. Ozdoganlar,“A Rotating-Tip-Based Mechanical Nano-Manufacturing Process:Nanomilling,” Nanoscale Research Letters 5, 1403-1407 (2010). (5) M. M.Hilali, A. Rohatgi, and B. To, “A Review and Understanding ofScreen-Printed Contacts and Selective-Emitter Formation,” 14^(th)Workshop on Crystalline Silicon Solar Cells and Modules, Winter Park,Colo., Aug. 8-11, 2004. (6) Marcie Black, Joanne Forzitai, Michael Jura,Jeff Miller, and Brian Murphy, “Electrical Contacts to NanostructuredAreas”, provisional patent application No. 61/536,243, attorney docketnumber 161565-0053, filed on Sep. 19, 2011.

All patents, patent applications, and publications mentioned in thisapplication are hereby incorporated by reference in their entireties.However, where a patent, patent application, or publication containingexpress definitions is incorporated by reference, those expressdefinitions should be understood to apply to the incorporated patent,patent application, or publication in which they are found, and not tothe remainder of the text of this application, in particular the claimsof this application.

What is claimed is:
 1. A silicon nanostructured device comprising: anon-nanostructured polycrystalline silicon substrate; a nanostructuredarea disposed on and contacting a surface of the substrate; a firstcontact comprising a comb-like pattern of metal directly electricallycontacting the nanostructured area; a p-n junction below thenanostructured area; and a second metal contact in electrical contactwith the substrate.
 2. The device of claim 1, suitable for use as asolar cell.
 3. The device of claim 1, wherein the nanostructures aremade from p-type silicon.
 4. The device of claim 1, wherein thenanostructures are made from n-type silicon.
 5. The device of claim 1,wherein lengths of nanostructures in the nanostructured area are betweenabout 150 nm and about 400 nm.
 6. The device of claim 4, whereinnanostructures in the nanostructured area have cross-sectional diametersbetween about 30 nm and about 200 nm.
 7. The device of claim 1, whereinone third to one half of a volume of the nanostructured area is silicon.8. The device of claim 1, wherein nanostructures in the nanostructuredareas are tapered such that bases of the nanostructures on average havelarger diameters than tips of the nanostructures.
 9. The device of claim1, wherein one of the first contact or the second contact comprisessilver.
 10. The device of claim 9, wherein the second metal contactcomprises aluminum.
 11. A silicon nanostructured device comprising: anon-nanostructured polycrystalline silicon substrate; a nanostructuredarea disposed on and contacting a surface of the substrate; apassivating layer coating the nanostructured area, the passivating layercomprising one of aluminum oxide, silicon dioxide, or silicon nitride; afirst contact comprising a comb-like pattern of metal directlyelectrically contacting the nanostructured area; a p-n junction belowthe nanostructured area; and a second contact in electrical contact withthe substrate.
 12. The device of claim 11, wherein at least one of thefirst contact or the second contact is fired at high temperature. 13.The device of claim 12, wherein the high temperature is in a range ofabout 700° C. to about 900° C.
 14. The device of claim 13, wherein thehigh temperature is in a range of about 775° C. to about 825° C.
 15. Thedevice of claim 12, wherein the device is heat dried before firing athigh temperature.
 16. The device of claim 15, wherein the device is heatdried at a temperature in a range of about 100° C. to about 200° C.before firing at high temperature.
 17. The device of claim 11, whereinthe non-nanostructured substrate comprises n-type silicon.
 18. Thedevice of claim 11, wherein the non-nanostructured substrate comprisesp-type silicon.